Stand-Alone Et錯上hernet Controller
Release Time：07/07/201女煙6
FEATURES &nb也煙sp; 火房; 西區 &nb國章sp; 得北; 師朋; 討河 弟做 務下; 花他; &nbs農件p; &n低鐘bsp;
機森; 看用; &見視nbsp; n5X5 mm, 32-pin QFN
山地; &nbs船哥p; &厭鐵nbsp; 來可 nCompatible with日日 Motorola SP唱開I SPEC
&nb學他sp; &nbs場見p; &n理請bsp; &n理兒bsp; lInput clock frequency 東月up to 60MHz
&nb就物sp; &少有nbsp; &熱生nbsp; lOnly support phase 0
&nb白舊sp; 路費 &nbs快放p; lOnly support計物 polarity 0
&nb藍綠sp; &nb笑大sp; &妹什nbsp; nIEEE 802.3 comp不開atible Ether靜離net controller
區東; &n知我bsp; &nb刀錯sp; 影樹; nFully compatible wit視東h 10/100 BASE-T 服市networks
&術開nbsp; 得視; &nbs員作p; &nbs你銀p; nIntegrated MAC a那家nd 10/100 PH坐到Y
&nb了樂sp; 輛睡; &n雪通bsp; 鄉黑 nSupports full a市服nd half dupl房些ex modes
討器; &nbs購自p; &n計還bsp; 外歌 nProgrammable padding 哥慢and CRC
&nbs還機p; &nb來爸sp; &黃我nbsp; 我不; generation
&nb鐵海sp; 路微; &nb藍子sp; nProgrammable padd藍制ing and CRC strippin坐民g
&nbs水新p; &nb多日sp; &n算用bsp; 秒商 nProgrammable flo從場w control
輛志 &n見這bsp; &nb你村sp; &nbs線匠p; nSupports Ethernet fram讀慢e length up to 1522 byt村還es
機西 年為 們土; 話身 nFlexible addres雪秒s filtering mode機車s
&n但話bsp; 車議; &nbs章歌p; &nbs鐘低p; n8k byte receive buffer
&n老地bsp; &nb如房sp; &nbs廠東p; &nbs看南p; n4k byte transmi費看t buffer
&nbs妹西p; &nbs議作p; &nb男遠sp; 木件; nMulti-function L和風ED output
&少分nbsp; &nbs去自p; &nbs什商p; &農服nbsp; n2.8V IO supply and 日吃1.2V core su還了pply
&nbs作通p; &n微工bsp; &n票間bsp; 請你 nCMOS process technolog費民y
2 ORDER INFORMATION&n劇的bsp; &請報nbsp; 兒熱; &知國nbsp; &n知高bsp; &n照好bsp; 短場; 舊生 &花明nbsp; &n就音bsp; &nb醫廠sp; &n快身bsp;
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Order Number
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Temperature Range
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Package
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Marking
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Packing Type
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AW6688TQR
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-40~85℃
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TRQ5x5-32L
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AW6688
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Tape & Reel
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3 OVERVIEW 光到; &nb有舊sp; &nb民都sp; 能個 &n鐵友bsp; &風舞nbsp; 熱章 &大窗nbsp; &nb樹對sp; &nb爸得sp; &小熱nbsp; 身高;
AW6688 is a st服筆andalone SPI to E道長thernet conve數生rter which serves兵志 as an Ethernet n但業etwork interface for an光務y controller with S懂筆PI master int購服erface. The SPI in們不terface is fully外生 compatible with MOTO S答司PI interface SPEC an近頻d only supports ph鐘信ase 0 and pol工藍arity 0 of the S錯電PI clock. The clo美白ck rate of the樹姐 SPI interfac工城e is up to 60MH知鐘z. A dedicated低什 interrupt ou好這tput is used林這 to communicate with 工文the SPI master chip. 商黑The Ethernet秒站 interface of AW風懂6688 is fully compatible站吧 with IEEE802.3 protocol謝城. A number of embedde工醫d filters are us熱藍ed to limit the i她厭ncoming Ethernet packe白中ts. Integrated hard他時ware CRC calculator he畫海lps to release the CP那唱U power of the master. 鐘微A 4k byte transmit buff到我er and an 8k b物風yte receive buffe音麗r is integrat聽購ed. Stream mode of trans視時ferring the Ethernet跳月 packets through th為慢e SPI interf對那ace is supports un音師der which the S問機PI transfer boundary can服好 be at any word boundar民門y of the Etherne務站t packets. The b人懂lock diagram of th區資e chip is shown bel得事ow.
相東 &nbs關黑p; &n照海bsp; Figure 1 AW6688 b厭低lock diagram
The function子這 of the major block of讀他 AW6688 is l自西isted below: MACspi_ifF技離rame dectx_fiforx能大_fifospi_regclk作都 & rstspi_南醫if_toprx data fifo白醫tx data fifotx stat 年來fifoReg interfacePH不錯Y
樂體 &麗兒nbsp; &綠國nbsp; &n都友bsp; nSPI_IF: the SPI_IF s聽公erves as the SPI protoc請他ol decoder and serial商暗 to parallel志從 converter.
&nbs畫那p; &nbs司老p; &吧影nbsp; &術人nbsp; nTX_FIFO, RX_FIFO聽事: the FIFO s雜朋ervers as the synchron司個izer between 南場the SPI clock d小她omain and the syst妹但em clock domain.學著
&n服哥bsp; 視文 事器 吃坐; nFRAME_DEC: the FRAME北讀_DEC decodes and enco麗商des the SPI packet, p草兒erforms the register熱歌 programming, recogniz人飛es the Ethernet pa議醫ckets and perfor計南ms the data transfe喝黑r between the 聽不internal data FI劇林FO.
要老 路照; &來匠nbsp; nSPI_REG: all the SPI城你 related registers an唱科d the interrupt related 分弟logic are implemented i師習n the SPI_REG物友
通錢 &nbs數土p; &森靜nbsp; &nb輛玩sp; nMAC: the MAC implemen喝金ts the IEEE802.3 co長高mpliant MAC logic.
&自黑nbsp; &nb好章sp; &nbs工師p; &說場nbsp; nPHY: the PHY perfor明計ms the data transfer bet嗎兒ween the analog in上視terface and the MA樹書C
